產(chǎn)品關(guān)鍵詞：
STM8AF5269,
Regulator OFF
This mode allows to power the device as soon as VDD reaches 1.8 V.
●
Regulator OFF/internal reset ON
This mode is available only on UFBGA package. It is activated by setting
BYPASS_REG and PDR_ON pins to VDD.
The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage
source through VCAP_1 and VCAP_2 pins, in addition to VDD.
The following conditions must be respected:
–VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
–
If the time for VCAP_1 and VCAP_2 to reach 1.08 V is faster than the time for VDD to
reach 1.8 V (VDD/VDDA minimum value of 1.7 V is obtained when the device
operates in the 0 to 70 °C temperature range and PDR is disabled), then PA0
should be connected to the NRST pin (see Figure 8). Otherwise, PA0 should be
asserted low externally during POR until VDD reaches 1.8 V (see Figure 9).
–If VCAP_1 and VCAP_2 go below 1.08 V and VDD is higher than 1.7 V, then a reset
must be asserted on PA0 pin.
In regulator OFF/internal reset ON mode, PA0 cannot be used as a GPIO pin since it
allows to reset the part of the 1.2 V logic which is not reset by the NRST pin, when the
internal voltage regulator in off.
●
Regulator OFF/internal reset OFF
This mode is available only on UFBGA package. It is activated by setting
BYPASS_REG pin to VDD and by applying an inverted reset signal to PDR_ON, and
allows to supply externally a 1.2 V voltage source through VCAP_1 and VCAP_2 pins, in
addition to VDD.
The following conditions must be respected:
–VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
–
PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach
1.08 V and until VDD reaches 1.8 V (see Figure 8).
–
NRST should be controlled by an external reset controller to keep the device
under reset when VDD is below 1.8 V (see Figure 9)
產(chǎn)品關(guān)鍵詞：
STM8AF5269,
![STM8AF5269/STM8AF528]()
